The present invention relates to a method for fabricating a semiconductor device of Group III nitride semiconductors.
A Group III nitride semiconductor, which is expressed by the general formula of Al.sub.x Ga.sub.1-x-y In.sub.y N (where 0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1 and x+y.ltoreq.1) has a direct-transition-type band structure with a band gap energy ranging from about 1.9 eV to about 6.2 eV and excels in thermal resistance. Therefore, semiconductor devices made of these Group III nitride semiconductors are currently under vigorous research and development. A semiconductor light-emitting device made of compound semiconductors mainly containing gallium nitride, for example, attracts increasing attention as a strong candidate for a light source of a next-generation high-density optical disk or a full-color LED display.
To improve the operating performance of such a light-emitting device made of Group III nitride semiconductors, it is extremely important how to form a p-type semiconductor layer with a low resistance.
Hereinafter, a conventional method for forming a p-type semiconductor layer and a semiconductor device using such a layer will be exemplified with reference to FIG. 10.
FIG. 10 illustrates a partial cross section of a conventional semiconductor device. As shown in FIG. 10, a buffer layer 102 of aluminum nitride (AlN) or gallium nitride (GaN) is formed on a sapphire substrate 101. A first semiconductor layer 103 of undoped GaN is formed on the buffer layer 102. A second semiconductor layer 104 of p-type GaN doped with magnesium (Mg) as an acceptor is formed on the first semiconductor layer 103. A p-side electrode 105 is formed on the second semiconductor layer 104 by alternately stacking nickel (Ni) and gold (Au) layers 105a and 105b one upon the other. In this example, only the method for forming the second semiconductor layer 104 will be specifically described and the illustration of an n-side electrode is omitted in FIG. 10.
Examples of the p-type dopant include magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr) and beryllium (Be). Among these elements, Mg and Zn are used particularly often.
Generally speaking, even if the second semiconductor layer 104 is doped with a p-type dopant, the p-type dopant can hardly act as an acceptor as it is (i.e., without any special treatment). Thus, the second semiconductor layer 104 is composed of intrinsic (i-type) crystals with a resistivity as high as 1.times.10.sup.8 .OMEGA.cm or more. It is believed that this is because hydrogen, which is released due to the decomposition of ammonium (NH.sub.3) gas used as a nitride source in growing the second semiconductor layer 104, is bonded to a p-type dopant such as Mg or Zn to inhibit the acceptor action of the dopant.
Thus, various methods for forming a p-type semiconductor layer by making the p-type dopant introduced act as an acceptor, i.e., by activating the dopant, have already been proposed.
According to a first exemplary method, the second semiconductor layer 104 doped with a p-type dopant is exposed to an electron beam as disclosed in Japanese Patent Publication for Opposition No. 6-9258.
A second exemplary method is disclosed in Japanese Laid-Open Publication No. 8-213656, for example. According to the second method, the second semiconductor layer 104 is heated up to about 800.degree. C. within an inert gas ambient.
The electrical energy of the electrons in the electron beam irradiated according to the first method or the thermal energy created according to the second method might dissociate hydrogen, which has been bonded to the p-type dopant such as Mg or Zn, from the dopant. Then, that dissociated hydrogen might detach itself from the second semiconductor layer 104, thereby possibly activating the p-type dopant as an acceptor.
According to a third exemplary method as disclosed in Japanese Laid-Open Publications Nos. 6-275868 and 10-163529, the second semiconductor layer 104 is annealed within nitrogen ambient and oxygen ambient, respectively, to activate Mg in the second semiconductor layer 104.
A fourth exemplary method is disclosed in Japanese Laid-Open Publication No. 10-144960, for example, in which the second semiconductor layer 104 is plasma annealed.
According to any of these proposed methods for forming a p-type semiconductor layer, the second semiconductor layer 104 shows a resistivity of about 1 .OMEGA.cm and a p-side electrode 105 can be in ohmic contact with the second semiconductor layer 104 at a contact resistivity of about 1.times.10.sup.-3 .OMEGA.cm.sup.2.
These conventional methods for forming a p-type semiconductor layer among Group III nitride semiconductor layers, however, have the following drawbacks.
According to the first method, the electron beam irradiated has a spot diameter of at most 50 to 60 .mu.m. Thus, when the substrate 101 has a size of approximately 2 centimeters square, it takes more than 10 hours to expose the entire upper surface of the second semiconductor layer 104 to the electron beam, or to finish processing a single substrate 101. Therefore, it is difficult to apply such a method to mass production, and it is impossible to process a plurality of substrates 101 in parallel.
Under the second and third methods, the second semiconductor layer 104 does not show p-type conductivity unless the temperature of the substrate is raised to as high as 600.degree. C. or higher. In annealing the substrate to raise its temperature to 600.degree. C. or higher, however, defects or cracking might be caused in the first or second semiconductor layer 103 or 104 depending on the thermal hysteresis before and after the annealing process. This is because the thermal expansion coefficient of the sapphire substrate 101 is much different from that of the first and second semiconductor layers 103 and 104 of GaN. In addition, if the temperature of the substrate 101 reaches 600.degree. C. or higher, nitrogen might detach itself from the first and second semiconductor layers 103 and 104 or Mg might thermally diffuse from the second semiconductor layer 104 into the first semiconductor layer 103, thus deteriorating the crystallinity of these semiconductor layers. As a result, the performance of the semiconductor device with such layers also deteriorates.
As for the fourth method, no specific details about plasma annealing are available from the disclosure of the above-cited reference.